18 search results - page 3 / 4 » Bus-aware microarchitectural floorplanning |
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
—Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the considera...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical ...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...