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ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
− This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time doma...
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
In this paper, we present a fast algorithm to derive the iiiharmonic distortion in fully balanced Gm- C filters. It is based on Vi i state-space modeling and decomposition of the f...
DSD
2008
IEEE
14 years 4 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
DATE
2005
IEEE
14 years 3 months ago
2005
IEEE
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
WOTUG
2008
13 years 11 months ago
2008
Abstract. This paper considers the issues involved in translating specifications described in the CSP B formal method into Handel-C. There have previously been approaches to transl...