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PPL
2008
185views more  PPL 2008»
13 years 10 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 8 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
DATE
2007
IEEE
108views Hardware» more  DATE 2007»
14 years 4 months ago
Speeding up SystemC simulation through process splitting
This paper presents a new approach that can be used to speed up SystemC simulations by automatically optimizing the model for simulation. The work addresses the inefficiency of th...
Youssef N. Naguib, Rafik S. Guindi
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
14 years 4 months ago
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao
IESS
2007
Springer
92views Hardware» more  IESS 2007»
14 years 4 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer