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GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 10 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
14 years 1 months ago
Automatically mapping applications to a self-reconfiguring platform
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
AIA
2007
13 years 11 months ago
Embedded harmonic control for dynamic trajectory planning on FPGA
This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated ...
Bernard Girau, Amine M. Boumaza
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 3 months ago
A TCP/IP Based Multi-device Programming Circuit
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
David V. Schuehler, Harvey Ku, John W. Lockwood