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DAC
1996
ACM
14 years 2 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
DAC
2006
ACM
14 years 11 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
14 years 4 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
EH
2003
IEEE
135views Hardware» more  EH 2003»
14 years 3 months ago
Towards Evolvable IP Cores for FPGAs
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
Lukás Sekanina
FPL
2006
Springer
147views Hardware» more  FPL 2006»
14 years 1 months ago
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration
A secure content distribution system is prototyped based on run-time partial reconfigurability of an FPGA. The system provides a robust content protection scheme for online conten...
Yohei Hori, Hiroyuki Yokoyama, Kenji Toda