869 search results - page 93 / 174 » Cache Architectures for Reconfigurable Hardware |
FPL
2007
Springer
14 years 3 months ago
2007
Springer
Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and...
MICRO
2007
IEEE
14 years 3 months ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Leakage energy will be the major energy consumer in future deep sub-micron designs. Especially the memory sub-system of future SOCs will be negatively affected by this trend. In o...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
FPL
2004
Springer
14 years 2 months ago
2004
Springer
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...