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DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 11 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
15 years 11 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
CASES
2003
ACM
15 years 11 months ago
Architectural optimizations for low-power, real-time speech recognition
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
DAC
2003
ACM
15 years 11 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
ATAL
2003
Springer
15 years 11 months ago
Constructing optimal policies for agents with constrained architectures
Optimal behavior is a very desirable property of autonomous agents and, as such, has received much attention over the years. However, making optimal decisions and executing optima...
Dmitri A. Dolgov, Edmund H. Durfee