4809 search results - page 52 / 962 » CajunBot: Architecture and algorithms |
ICCD
2006
IEEE
14 years 8 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
ISLPED
2003
ACM
14 years 4 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
GLVLSI
2000
IEEE
14 years 3 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
IPPS
2003
IEEE
14 years 4 months ago
2003
IEEE
Aim of the paper is to develop a concise but comprehensive analytical model for the well-known Grace Hash Join algorithm on cost effective cluster architectures. This approach is ...
ASIACRYPT
2001
Springer
14 years 3 months ago
2001
Springer
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...