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VTS
2006
IEEE
101views Hardware» more  VTS 2006»
14 years 3 months ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
DAC
2000
ACM
14 years 10 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
VLSI
2012
Springer
12 years 4 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
DAC
2003
ACM
14 years 10 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
DAC
2003
ACM
14 years 10 months ago
An IDF-based trace transformation method for communication refinement
In the Artemis project [13], design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mappin...
Andy D. Pimentel, Cagkan Erbas