285 search results - page 14 / 57 » Cell architecture for nanoelectronic design |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
SIGCOMM
2010
ACM
13 years 7 months ago
2010
ACM
Reducing the energy consumption of a wireless cellular network is an important and urgent problem. This paper studies the effect of cell sizes on the energy consumed by the networ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Battery lifetime and safety are primary concerns in the design of battery operated systems. Lifetime management is typically supervised by the system via battery-aware task schedu...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...