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» Cell architecture for nanoelectronic design
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DAC
1999
ACM
14 years 8 months ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel
DAC
2002
ACM
14 years 8 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
DAC
2004
ACM
14 years 8 months ago
Multiple constant multiplication by time-multiplexed mapping of addition chains
An important primitive in the hardware implementations of linear DSP transforms is a circuit that can multiply an input value by one of several different preset constants. We prop...
James C. Hoe, Markus Püschel, Peter Tummeltsh...
SIGMETRICS
2008
ACM
13 years 7 months ago
Traffic capacity of multi-cell WLANS
Performance of WLANs has been extensively studied during the past few years. While the focus has mostly been on isolated cells, the coverage of WLANs is in practice most often rea...
Thomas Bonald, Ali Ibrahim, James Roberts
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
14 years 4 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili