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» Cell architecture for nanoelectronic design
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EL
2008
166views more  EL 2008»
13 years 7 months ago
The digital library as an enterprise: the Zachman approach
Purpose: Examines the needs of digital library stakeholders and how a collaborative digital library might be designed to meet these needs. The collaborative digital library has be...
Abdullah Abrizah, A. N. Zainab
ARITH
2009
IEEE
14 years 2 months ago
A 32-bit Decimal Floating-Point Logarithmic Converter
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calc...
Dongdong Chen, Yu Zhang, Younhee Choi, Moon Ho Lee...
IEEECGIV
2006
IEEE
14 years 1 months ago
Real-Time Tracking with Non-Rigid Geometric Templates Using the GPU
The tracking of features in real-time video streams forms the integral part of many important applications in human-computer interaction and computer vision. Unfortunately trackin...
Julius Fabian Ohmer, Frédéric Maire,...
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 23 days ago
A highly regular multi-phase reseeding technique for scan-based BIST
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
14 years 1 months ago
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....