170 search results - page 5 / 34 » Challenges in Embedded Memory Design and Test |
IPPS
2000
IEEE
14 years 2 months ago
2000
IEEE
We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
DAC
1999
ACM
14 years 2 months ago
1999
ACM
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC . The novel feature of the approach is the use an embedde...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
CF
2009
ACM
14 years 4 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...