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» Challenges in Physical Chip Design
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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 21 days ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
14 years 6 days ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
MOBICOM
2006
ACM
14 years 2 months ago
Localization in underwater sensor networks: survey and challenges
In underwater sensor networks (UWSNs), determining the location of every sensor is important and the process of estimating the location of each node in a sensor network is known a...
Vijay R. Chandrasekhar, Winston Khoon Guan Seah, Y...
PERSUASIVE
2010
Springer
13 years 7 months ago
Animate Objects: How Physical Motion Encourages Public Interaction
The primary challenge for information terminals, kiosks, and incidental use systems of all sorts, is that of getting the “first click” from busy passersby. This paper presents ...
Wendy Ju, David Sirkin
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
14 years 2 months ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...