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DAC
2002
ACM
14 years 12 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 7 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
14 years 5 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 5 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
BROADNETS
2006
IEEE
14 years 5 months ago
An Energy Efficient and Accurate Slot Synchronization Scheme for Wireless Sensor Networks
Existing slotted channel access schemes in wireless networks assume that slot boundaries at all nodes are synchronized. In practice, relative clock drifts among nodes cause slot mi...
Lillian Dai, Prithwish Basu, Jason Redi