509 search results - page 19 / 102 » Chip Multi-Processor Generator |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
NOCS
2007
IEEE
14 years 2 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
MJ
2011
13 years 3 months ago
2011
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
DSD
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...