509 search results - page 25 / 102 » Chip Multi-Processor Generator |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
This work focuses on communication architecture analysis for multi-processor Systems-on-Chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-proc...
FCCM
1997
IEEE
14 years 7 days ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...