Sciweavers

236 search results - page 25 / 48
» Chordal Topologies for Interconnection Networks
Sort
View
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
14 years 23 days ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
NOCS
2009
IEEE
14 years 3 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
MICRO
2008
IEEE
116views Hardware» more  MICRO 2008»
14 years 3 months ago
Power reduction of CMP communication networks via RF-interconnects
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyu...
ICDCS
2005
IEEE
14 years 2 months ago
FraNtiC: A Fractal Geometric Framework for Mesh-Based Wireless Access Networks
The design of the access networks of next generation broadband wireless systems requires special attention in the light of changing network characteristics. In this paper, we pres...
Samik Ghosh, Kalyan Basu, Sajal K. Das
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
14 years 3 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...