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» Circuit Bipartitioning Using Genetic Algorithm
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DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 5 months ago
Simulation-based reusable posynomial models for MOS transistor parameters
We present an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the Geometric P...
Varun Aggarwal, Una-May O'Reilly
FPL
2004
Springer
94views Hardware» more  FPL 2004»
14 years 4 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
14 years 3 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
IJON
2006
76views more  IJON 2006»
13 years 11 months ago
Evolving networks of integrate-and-fire neurons
This paper addresses the following question: ``What neural circuits can emulate the monosynaptic correlogram generated by a direct connection between two neurons?'' The ...
Francisco J. Veredas, Francisco J. Vico, Jos&eacut...
EH
2003
IEEE
117views Hardware» more  EH 2003»
14 years 4 months ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan