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ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
13 years 12 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
14 years 5 days ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
GECCO
2004
Springer
123views Optimization» more  GECCO 2004»
14 years 1 months ago
A Hybrid Genetic Approach for Circuit Bipartitioning
We propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic whic...
Jong-Pil Kim, Yong-Hyuk Kim, Byung Ro Moon
FPGA
1998
ACM
132views FPGA» more  FPGA 1998»
13 years 12 months ago
Circuit Partitioning with Complex Resource Constraints in FPGAs
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
Huiqun Liu, Kai Zhu, D. F. Wong
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
13 years 12 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel