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ISMVL
2010
IEEE
158views Hardware» more  ISMVL 2010»
13 years 11 months ago
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...
Alexander Finder, Rolf Drechsler
DAC
2004
ACM
14 years 27 days ago
Hierarchical approach to exact symbolic analysis of large analog circuits
—This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing s...
Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi
ASPDAC
2007
ACM
117views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks
Abstract-- We present the short-circuit code transformation technique, intended for embedded compilers. The transformation technique optimizes conditional blocks in high-level prog...
Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
14 years 23 days ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 23 days ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...