191 search results - page 5 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ISQED
2008
IEEE
14 years 4 months ago
2008
IEEE
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
ISPD
2010
ACM
14 years 4 months ago
2010
ACM
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
DFT
1997
IEEE
14 years 2 months ago
1997
IEEE
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...