6 search results - page 1 / 2 » Clock tree synthesis with data-path sensitivity matching |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— In this paper, we have proposed a thermal aware routing based parameterization to generate a clock model that takes the stochastic temperature variation into consideration. The...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...