A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon,...
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K...
—This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transc...
S. P. Voinigescu, S. T. Nicolson, M. Khanpour, K. ...
A number of methods are presentedfor highly efficient calculation of substratecurrenttransport. A three-dimensionalGreen'sFunction based substrate representation, in combinat...
Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sang...
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...