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DATE
2003
IEEE
115views Hardware» more  DATE 2003»
14 years 2 months ago
Control Flow Driven Splitting of Loop Nests at the Source Code Level
This paper presents a novel source code transformation for control flow optimizationcalled loop nest splitting which minimizes the number of executed if-statements in loop nests ...
Heiko Falk, Peter Marwedel
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 2 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
14 years 3 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 5 months ago
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption....
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 2 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...