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CODES
2008
IEEE
14 years 1 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
HPCC
2009
Springer
13 years 11 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
DAC
2008
ACM
14 years 7 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
LCPC
2007
Springer
14 years 25 days ago
A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor
This paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several servi...
Jairo Balart, Marc González, Xavier Martore...
HIPEAC
2007
Springer
14 years 25 days ago
Compiler-Assisted Memory Encryption for Embedded Processors
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy