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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 4 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 11 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ASPDAC
2009
ACM
111views Hardware» more  ASPDAC 2009»
14 years 2 months ago
A UML-based approach for heterogeneous IP integration
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
Zhenxin Sun, Weng-Fai Wong
DATE
2009
IEEE
140views Hardware» more  DATE 2009»
14 years 2 months ago
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors
Carbon Nanotube Field-Effect Transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits o...
Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei