10891 search results - page 12 / 2179 » Combining Model Reductions |
DATE
1999
IEEE
14 years 1 hour ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further ex...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
CVPR
2009
IEEE
15 years 2 months ago
2009
IEEE
We introduce a new technique that can reduce any
higher-order Markov random field with binary labels into
a first-order one that has the same minima as the original.
Moreover, w...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...