415 search results - page 32 / 83 » Comparative evaluation of memory models for chip multiproces... |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
RTAS
2006
IEEE
2006
IEEE
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
14 years 1 months ago
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...
LPNMR
2009
Springer
2009
Springer
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
14 years 2 months ago
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...