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TVLSI
2008
120views more  TVLSI 2008»
13 years 7 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CDC
2010
IEEE
116views Control Systems» more  CDC 2010»
13 years 2 months ago
High level model predictive control for plug-and-play process control with stability guaranty
In this paper a method for designing a stabilizing high level model predictive controller for a hierarchical plugand-play process is presented. achieved by abstracting the lower la...
Axel Gottlieb Michelsen, Jakob Stoustrup
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 1 months ago
An ILP Formulation for Reliability-Oriented High-Level Synthesis
Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulatio...
Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Er...
FPL
2000
Springer
116views Hardware» more  FPL 2000»
13 years 11 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 11 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana