622 search results - page 13 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
ESTIMEDIA
2008
Springer
13 years 9 months ago
2008
Springer
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
SBACPAD
2003
IEEE
14 years 19 days ago
2003
IEEE
Traffic monitoring and analysis based on general purpose systems with high speed interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, requires carefully designed software...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
ISCAS
2002
IEEE
14 years 8 days ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...