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DATE
2008
IEEE
148views Hardware» more  DATE 2008»
14 years 3 months ago
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications
Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot b...
Mark Muir, Tughrul Arslan, Iain Lindsay
ASPDAC
2001
ACM
185views Hardware» more  ASPDAC 2001»
14 years 19 days ago
Power optimization and management in embedded systems
Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...
Massoud Pedram
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 3 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
CODES
2007
IEEE
14 years 3 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
14 years 3 months ago
FPGA-based architecture for real-time IP video and image compression
–Three-dimensional imaging applications require high resolution images that finally result in high data volumes. Due to bandwidth and storage restrictions, an efficient and robus...
Dimitris Maroulis, Nikos Sgouros, Dionisis Chaikal...