1198 search results - page 116 / 240 » Compiling for EDGE Architectures |
115
Voted
ASPLOS
2010
ACM
15 years 10 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...
143
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MICRO
2007
IEEE
15 years 9 months ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
132
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SPAA
2006
ACM
15 years 9 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
240
Voted
MICRO
2000
IEEE
15 years 3 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
144
Voted
TCAD
2002
15 years 3 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...