1133 search results - page 26 / 227 » Compiling for Speculative Architectures |
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
MICRO
2000
IEEE
14 years 24 days ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
SBACPAD
2007
IEEE
14 years 2 months ago
2007
IEEE
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...