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PATMOS
2005
Springer
14 years 1 months ago
A Power-Efficient and Scalable Load-Store Queue Design
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
Fernando Castro, Daniel Chaver, Luis Piñuel...
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
13 years 11 months ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
14 years 24 days ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
CALCO
2007
Springer
202views Mathematics» more  CALCO 2007»
14 years 1 months ago
Algebraic Models of Simultaneous Multithreaded and Multi-core Processors
Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state...
Neal A. Harman
HPCA
2006
IEEE
14 years 8 months ago
Construction and use of linear regression models for processor performance analysis
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...