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FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 2 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
ICSE
2001
IEEE-ACM
14 years 1 months ago
Theory of Software Reliability Based on Components
We present a foundational theory of software system reliability based on components. The theory describes how component developers can design and test their components to produce ...
Richard G. Hamlet, David V. Mason, Denise M. Woit
UIST
1999
ACM
14 years 1 months ago
Supporting Awareness and Interaction Through Collaborative Virtual Interfaces
This paper explores interfaces to virtual environments supporting multiple users. An interface to an environment allowing interaction with virtual artefacts is constructed, drawin...
Mike Fraser, Steve Benford, Jon Hindmarsh, Christi...
ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
14 years 1 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
14 years 22 days ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...