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DAC
2011
ACM
12 years 9 months ago
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...
Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, ...
INTEGRATION
2008
101views more  INTEGRATION 2008»
13 years 10 months ago
An efficient terminal and model order reduction algorithm
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...
DAC
2008
ACM
14 years 11 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
VISUALIZATION
2000
IEEE
14 years 2 months ago
Navigating high-dimensional spaces to support design steering
Throughout the design cycle, visualization, whether a sketch scribbled on the back of a spare piece of paper or a fully detailed drawing, has been the mainstay of design: we need ...
Helen Wright, Ken Brodlie, Tim David
DAC
2010
ACM
14 years 1 months ago
Coverage in interpolation-based model checking
Coverage is a means to quantify the quality of a system specification, and is frequently applied to assess progress in system validation. Coverage is a standard measure in testin...
Hana Chockler, Daniel Kroening, Mitra Purandare