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GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Timing-driven N-way decomposition
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...
David Bañeres, Jordi Cortadella, Michael Ki...
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 8 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
ICCAD
2003
IEEE
109views Hardware» more  ICCAD 2003»
14 years 4 months ago
Large-Scale Circuit Placement: Gap and Promise
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie,...
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
DAC
2007
ACM
14 years 8 months ago
TROY: Track Router with Yield-driven Wire Planning
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan