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» Concurrent Fault Detection in Random Combinational Logic
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VTS
2006
IEEE
93views Hardware» more  VTS 2006»
14 years 21 days ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
ICRA
2007
IEEE
151views Robotics» more  ICRA 2007»
14 years 1 months ago
Sensor Analysis for Fault Detection in Tightly-Coupled Multi-Robot Team Tasks
— This paper presents a sensor analysis based fault detection approach (which we call SAFDetection) that is used to monitor tightly-coupled multi-robot team tasks. Our approach a...
Xingyan Li, Lynne E. Parker
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 8 days ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 1 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand