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162
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VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
15 years 12 days ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
101
Voted
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 9 months ago
A scalable method for the generation of small test sets
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
Santiago Remersaro, Janusz Rajski, Sudhakar M. Red...
107
Voted
DATE
1998
IEEE
92views Hardware» more  DATE 1998»
15 years 6 months ago
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis...
FATES
2004
Springer
15 years 6 months ago
Test Generation Based on Symbolic Specifications
Abstract. Classical state-oriented testing approaches are based on simple machine models such as Labelled Transition Systems (LTSs), in which data is represented by concrete values...
Lars Frantzen, Jan Tretmans, Tim A. C. Willemse
144
Voted
CP
2009
Springer
15 years 5 months ago
Constraint-Based Local Search for the Automatic Generation of Architectural Tests
Abstract. This paper considers the automatic generation of architectural tests (ATGP), a fundamental problem in processor validation. ATGPs are complex conditional constraint satis...
Pascal Van Hentenryck, Carleton Coffrin, Boris Gut...