Sciweavers

734 search results - page 79 / 147
» Configurable Transactional Memory
Sort
View
FPGA
2006
ACM
116views FPGA» more  FPGA 2006»
14 years 14 days ago
Performance benefits of monolithically stacked 3D-FPGA
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wo...
CODES
2001
IEEE
14 years 13 days ago
A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
William Fornaciari, Donatella Sciuto, Cristina Sil...
TCAD
2002
86views more  TCAD 2002»
13 years 8 months ago
Platune: a tuning framework for system-on-a-chip platforms
System-on-a-chip (SOC) platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's ap...
Tony Givargis, Frank Vahid
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
14 years 3 months ago
Architecture Exploration of NAND Flash-based Multimedia Card
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
Sungchan Kim, Chanik Park, Soonhoi Ha
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 2 months ago
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Abstract- This paper proposes a hardwadsoftware cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG correspondingto an application program and a timing ...
Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa,...