This paper presents a novel approach to particle filtering which minimizes the total tracking distortion by considering dynamic variance of proposal density and adaptive number o...
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...