In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
-- We describe a new high-level compiler called Integral fordesigning system interface modules. The inputis a high-levelconcurrent algorithmic specification that can model complex ...
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Legged autonomous vehicles move by executing patterns of leg-joint angles known as gaits. Synthesizing gaits by hand is a complex and time-consuming task which becomes even more c...
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-dr...