3 search results - page 1 / 1 » Controller Estimation for FPGA Target Architectures during H... |
ISSS
2002
IEEE
14 years 4 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
ISQED
2007
IEEE
14 years 5 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DAC
2006
ACM
15 years 5 days ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...