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» Core-Selectability in Chip Multiprocessors
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172
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IEEEPACT
2009
IEEE
15 years 1 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
127
Voted
DSD
2003
IEEE
121views Hardware» more  DSD 2003»
15 years 9 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
127
Voted
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
15 years 8 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
119
Voted
EUROPAR
1997
Springer
15 years 8 months ago
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, K...
ISLPED
2005
ACM
123views Hardware» more  ISLPED 2005»
15 years 9 months ago
Coordinated, distributed, formal energy management of chip multiprocessors
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...