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CODES
2011
IEEE
12 years 10 months ago
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
WORDS
2003
IEEE
14 years 3 months ago
A Framework for Scalable Analysis and Design of System-wide Graceful Degradation in Distributed Embedded Systems
We present a framework that will enable scalable analysis and design of graceful degradation in distributed embedded systems. We define graceful degradation in terms of utility. A...
Charles P. Shelton, Philip Koopman, William Nace
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
14 years 1 months ago
Power analysis and low-power scheduling techniques for embedded DSP software
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, M...
IWPC
2000
IEEE
14 years 2 months ago
Automated Quality Analysis of Component Software for Embedded Systems
The Java programming language has gained increasing importance for the development of embedded systems. To be cost efficient, such systems have to cope with significant hardware...
Jens H. Jahnke, Jörg Niere, Jörg P. Wads...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...