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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 1 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles
ITC
1996
IEEE
114views Hardware» more  ITC 1996»
13 years 11 months ago
A Demonstration IC for the P1149.4 Mixed-Signal Test Standard
The P1149.4 mixed-signal boundary scan standard is demonstrated with a CMOS integrated circuit. Design issues and characterization data are presented.
Keith Lofstrom
IJON
2010
148views more  IJON 2010»
13 years 4 months ago
Integration of heterogeneous data sources for gene function prediction using decision templates and ensembles of learning machin
Several solutions have been proposed to exploit the availability of heterogeneous sources of biomolecular data for gene function prediction, but few attention has been dedicated t...
Matteo Re, Giorgio Valentini
ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
13 years 5 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 4 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...