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DFT
1997
IEEE
108views VLSI» more  DFT 1997»
14 years 23 days ago
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Ma...
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
14 years 1 months ago
Analog IP Testing: Diagnosis and Optimization
In this paper, we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in th...
Carlo Guardiani, Patrick McNamara, Lidia Daldoss, ...
DAC
2006
ACM
14 years 9 months ago
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. ali...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 5 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
14 years 9 days ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng