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» Critical path analysis of the TRIPS architecture
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IEEEPACT
1999
IEEE
13 years 11 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
DAC
2004
ACM
13 years 11 months ago
A methodology to improve timing yield in the presence of process variations
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wa...
DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 4 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
ICWN
2007
13 years 9 months ago
PBR: Priority Based Routing in Multi-Sink Sensor Networks
- Wireless sensor networks have been widely used in many fields with the developments of the related techniques. But there are many problems in traditional single sink sensor netwo...
Min Meng, Hui Xu, Xiaoling Wu, Brian J. d'Auriol, ...