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ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 11 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He
DATE
2003
IEEE
76views Hardware» more  DATE 2003»
14 years 23 days ago
Modeling and Evaluation of Substrate Noise Induced by Interconnects
Interconnects have deserved attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. In this paper, we evaluate the importa...
Ferran Martorell, Diego Mateo, Xavier Aragon&egrav...
PATMOS
2007
Springer
14 years 1 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ISLPED
2003
ACM
142views Hardware» more  ISLPED 2003»
14 years 21 days ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
David Nguyen, Abhijit Davare, Michael Orshansky, D...
TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...